High-Performance 10-kV-Rated, 175-mΩ 4H-SiC MOSFETs With MeV JFET Implantation and Efficient Termination

作者：Lingxu Kong, Sizhe Chen, Na Ren, Manyi Ji, Yanjun Li, Haidong Yan, Z.S. Liu, Hongyi Xu, Cheng Ji, Xiuyan Lin, Xueqian Zhong, Wei Chen, Haitao Huang, Yongxi Zhang, Kuang Sheng · 发表于：IEEE Transactions on Electron Devices · 年份：2025 · DOI：10.1109/ted.2025.3574110 · 被引用次数：7 · 研究领域：Silicon Carbide Semiconductor Technologies、Semiconductor materials and devices、Multilevel Inverters and Converters

This article presents the successful development of high-performance 10-kV-rated, 175-mΩ 4H-SiC MOSFETs with a JFET design width of 0.8–1.2 μm, an active area of 0.67 cm2, and a chip size of 1 cm2. Featuring a three-zone junction termination extension (3-JTE) structure with a total length of 350 μm, the device demonstrates a superior blocking performance exceeding 12 kV. A key challenge in high-voltage SiC MOSFET design is balancing the reduction of JFET width (WJFET)—critical for lowering the gate oxide electric field and improving long-term reliability—against the adverse effects of Al ion implantation straggle, which increases JFET resistance. To address this, we optimized the p-well and JFET implantation processes, employing both simulation and experimental validation. The fabricated device achieves the highest rated current and the smallestWJFETreported to date among 1-kV-rated SiC MOSFETs. Additionally, this article discusses the characteristics of the 10-kV-rated device and offers a comparative analysis of device performance under various fabrication processes. Detailed implementation schemes and final device performance are presented, paving the way for the commercialization of large-area, ultrahigh-voltage (UHV) SiC MOSFETs and enhancing the feasibility of large-scale production for next-generation power electronics applications.