Mid-BEOL Heterogeneous Integration Through Sub-1um Pitch Hybrid Bonding & Advanced Silicon Carrier Technologies for AI & Compute Applications

作者：A. Elsherbini, Tushar Talukdar, Thomas Sounart, S. Chauhan, K. Radhakrishnan, Yi Shi, Haris Khan Niazi, P. Nordeen, A. Vyatskikh, Brandon Rawlings, W. Brezinski, R. Vreeland, Sou-Chi Chang, Feras Eid, S. Liff, J. Swan · 发表于：Electronic Components and Technology Conference · 年份：2025 · DOI：10.1109/ectc51687.2025.00133 · 被引用次数：5

Mid-BEOL integration where chiplets or active/passive layers are integrated within the BEOL (back end of line) of a base wafer can offer significant benefits over traditional 3D packaging in many architectures, especially in the AI era. New technology elements developed in the past few years made this possible in a high-volume manufacturing environment. In this paper, we will review these technologies in the context of this application and highlight the technology and integration requirements and their challenges. We will also cover three example applications: (1) active devices as part of the BEOL which can offer >2X improvement in on-die memory density as well as support for heterogeneous memory technologies with integration capabilities comparable to monolithically integrated memories, (2) on-chip local power conversion with $>2 X$ reduced resistance parasitics and opportunity for independently optimized power transistors. and (3) ex-situ fabrication of high-density capacitors for power conversion and DC decoupling enabling integration of novel materials independently without the processing limits of insitu integration.