Dimension Influence on the Interface Fatigue Characteristics of Three-Dimensional TSV Array: A Fully Coupled Thermal-Electrical-Structural Analysis

作者：Kaihong Hou, Zhengwei Fan, Shufeng Zhang, Yashun Wang, Xun Chen · 发表于：IEEE Transactions on Device and Materials Reliability · 年份：2024 · DOI：10.1109/tdmr.2024.3453923 · 被引用次数：6 · 研究领域：3D IC and TSV technologies、Electronic Packaging and Soldering Technologies、Electrostatic Discharge in Electronics

As the interconnected structure of 3D chip, through-silicon via undertakes the key functions in energy transmission, mechanical support and signal transmission of 3D chip. With the increasing of TSV interconnection density, the reliability of TSV is becoming increasingly prominent, and the slight variation of TSV dimension may exert severe impact on the fatigue life of the TSV array. In this study, a typical double-layer TSV interconnected 3D array is built to carried out the multi-interface fatigue analysis under thermoelectric structure coupling field, the influence of different dimension of the TSV interconnected array on the fatigue life of various interface and whole thermoelectric circuit are deeply investigated. Results shows that: 1) relatively small or large diameter of TSV-Cu or Bump can effectively improve the fatigue life of Bump-RDL interface. 2) The fatigue life of the top interface between TSV-Cu and SiO2 layer is slightly higher than that of the bottom interface. 3) The optimal dimension combination of TSV interconnected array is highly related with external working environment and own working state. Under the condition of this study, the dimension corresponding to Case 0 (TSV-Cu diameter:$5~\mu $m, Bump diameter:$10~\mu $m, Pitch:$100~\mu $m, SiO2 layer thickness:$1~\mu $m) is the optimal solution. 4) TSV-Cu diameter and SiO2 thickness have the greatest influence on the fatigue life of TSV array. Relevant results can provide valuable references for locating t...