Advancing Monolayer 2-D nMOS and pMOS Transistor Integration From Growth to Van Der Waals Interface Engineering for Ultimate CMOS Scaling

作者：C. J. Dorow, Kevin O'Brien, Carl H. Naylor, Sudarat Lee, Ashish Verma Penumatcha, Andy Hsiao, Tristan A. Tronic, Michael Christenson, K. Maxey, Hui Zhu, A. Oni, Urusa S. Alaan, Tanay A. Gosavi, Arnab Sen Gupta, Robert Bristol, Scott B. Clendenning, M. Metz, Uygar E. Avci · 发表于：IEEE Transactions on Electron Devices · 年份：2021 · DOI：10.1109/ted.2021.3118659 · 被引用次数：5 · 研究领域：2D Materials and Applications、Nanowire Synthesis and Applications、Advancements in Semiconductor Devices and Circuit Design

2-D-material channels enable ultimate scaling of MOSFET transistors and will help Moore’s Law scaling for years. We demonstrate the state of both n- and p-MOSFETs using monolayer transition metal dichalcogenide (TMD) channels of sub-1 nm thickness and manufacturable CVD, molecular beam epitaxy (MBE), or seeded growth. nMOS devices on transferred MBE MoS2using novel contact metal show low variation, one of the lowest reported contact resistances (${R}_{\text {c}}$) of 0.4$\text{k}\Omega \cdot \mu \text{m}$, low hysteresis, and good subthreshold swing (SS) of 77 mV/dec. pMOS devices using CVD WSe2show 89 mV/dec SS, best reported for pMOS on grown films, but ON-current remains behind nMOS. We show${R}_{\text {C}}$is improved by$5\times $by using a bake process prior to contact metal deposition. Transfer-free, area-selective seeded growth techniques for WS2and MoS2are demonstrated as options for wafer-scale TMD channel growth. WS2transistors achieve 10$\mu \text{A}/\mu \text{m}$ON-current, highest reported on WS2using seeded growth. A new capacitance method is shown to monitor 2-D material contact interface quality. Gate-oxide interface engineering through metal seeding and atomic layer deposition (ALD) demonstrates that a single 2-D channel material can selectively make pMOS or nMOS transistors, alike Si CMOS, and can also be used as a method to achieve p-type doping. We compare back-gated bare channel devices with dual-gate devices and observe hysteresis-free operation and an i...