Scalable Reconfigurable Circuits with Double-Gate MoS 2 Transistors

作者：Kuanglei Chen, Yu Geng, Jiankun Xiao, Hongyun Zhao, Jinsen Shang, He Jiang, Xiaoyu He, Jianhua Zhang, Weiheng You, Xun Zhang, Zheng Zhang, Yue Zhang · 发表于：ACS Nano · 年份：2026 · DOI：10.1021/acsnano.6c02873 · 被引用次数：2 · 研究领域：Low-power high-performance VLSI design、Advanced Memory and Neural Computing、Neural Networks and Reservoir Computing

Reconfigurable transistors are essential for the development of high-efficiency and high-versatility logic circuits. Present reconfigurable devices primarily achieve more functionality by integrating additional control dimensions which significantly improves area efficiency. However, the reliability issues and fabrication difficulty arising from increased device complexity, along with the critical problem of input/output voltage mismatch, severely limit their cascadability and scalability. Here, we propose a cascadable reconfigurable logic unit based on MoS 2 double-gate transistors (DGFETs), which is compatible with conventional integration processes, enabling large-scale fabrication. A 10 × 10 array was successfully demonstrated─representing the largest array to date in the field of two-dimensional reconfigurable transistors for logic. By utilizing double-gate tuning combined with the resistive voltage division mechanism of the inverter, the unit achieves four distinct logic functions using only an n-type channel, while maintaining complete matching of input and output voltage range. Furthermore, we fabricated reconfigurable circuits with XOR/XNOR function through cascaded connections and demonstrated real-time switching between half-subtractor and comparator operations, thereby fully showcasing the unit’s potential of cascading. This work provides a viable and practical approach toward the scalable integration of reconfigurable transistors.