Compact Modeling of Process Variation and Reliability Predictions for Nanosheet Gate-All-Around FET

作者：Mengge Jin, Chao Wang, Siyi Xu, Yang Shen, Yuhang Zhang, Bingyi Ye, Shaoqiang Chen, Xinyu Dong, Fei Lu, Ziyu Liu, Xiaojin Li, Yanling Shi, Yabin Sun · 发表于：IEEE Transactions on Device and Materials Reliability · 年份：2025 · DOI：10.1109/tdmr.2025.3589379 · 被引用次数：1 · 研究领域：Semiconductor materials and devices、Advancements in Semiconductor Devices and Circuit Design、Integrated Circuits and Semiconductor Failure Analysis

In this work, a semi-analytical compact model is developed to quantify the impact of random process variations on nanosheet field-effect transistors (NSFETs) at the 3nm technology node. Three primary sources of variability work function variation (WFV), line width roughness (LWR), and gate edge roughness (GER) are systematically analyzed. By extracting and calibrating empirical parameters, the proposed model accurately captures the statistical trends of process-induced fluctuations across a broad range of conditions. The model is integrated into the BSIM-CMG framework for circuit-level variability assessment, enabling comprehensive evaluation of performance deviations. Simulation results indicate that WFV dominates the overall reliability degradation, leading to energy variations from –12% to +24%. This study provides a refined predictive framework for assessing process-induced reliability risks and optimizing circuit design in advanced semiconductor technologies.