Design and Fabrication of a Novel 1200 V 4H-SiC Trench MOSFET With Periodically Grounded Trench Bottom Shielding

作者：Jun Yuan, Wei Chen, Fei Guo, Kuan Wang, Zhijie Cheng, Yangyang Wu, Shaodong Xu, Rong Zhang, Guoqing Xin, Zhiqiang Wang · 发表于：IEEE Transactions on Electron Devices · 年份：2025 · DOI：10.1109/ted.2025.3559888 · 被引用次数：10 · 研究领域：Silicon Carbide Semiconductor Technologies、Semiconductor materials and devices、Multilevel Inverters and Converters

In this article, a silicon carbide (SiC) trench MOSFET with periodically grounded p-type shielding region (P+SLD) at the trench bottom (PGP-TMOS) is designed and experimentally demonstrated. There exist deep-implanted P+ (DP) regions on both sides of the trench and the P+SLD is grounded by connecting to the DP region periodically. Therefore, the PGP-TMOS owns two different schematic cross section views. The P+SLD and DP region together improve the robustness of the gate oxide. A current spreading layer (CSL) by epitaxy is introduced to improve the device performance. Numerical 2D-simulation results show that compared with the trench MOSFET with floating P+SLD (FP-TMOS), the peak electric field in the gate oxide (Eox,peak)is decreased by 50.77% while the breakdown voltage (BV) and specific ON-resistance (Ron,sp)keep almost the same. In addition, the PGP-TMOS demonstrates superior switching characteristics. The PGP-TMOS has been manufactured on different wafers. When single epitaxial wafers are used, BV of the samples is only 1300 V and the conduction characteristic is poor due to the junction field-effect transistor (JFET) effect and ion implantation scattering. BV andRon,spare improved to 1570 V and 5.96 mΩ⋅cm2, respectively, when the PGP-TMOS is manufactured on wafers with a CSL layer introduced by epitaxy. BV andRon,spare improved by 20.77% and 91.85%, respectively, compared with the former ones. Moreover, the influence of the key parameters on the PGP-TMOS is discussed, wh...