A 0.024mm 2 All-Digital Fractional Output Divider with 257fs Worst-Case Jitter Using Split-DTC-Based Background Calibration

作者：Y. Yu, Deng Luo, Jianjun Chen, Yang Guo, Bin Liang, Yaqing Chi, Hanhan Sun, Jing Xiao, Hao Gao, Tao Ming, Kai Tang · 年份：2025 · DOI：10.1109/isscc49661.2025.10904505 · 被引用次数：6 · 研究领域：Advancements in PLL and VCO Technologies、Photonic and Optical Devices、Analog and Mixed-Signal Circuit Design

In modern system-on-chips (SoCs), compact, low-jitter and low-power on-chip clock generators are essential for delivering multiple output frequencies to various modules, including microprocessors, IO interfaces, and power-management systems. Conventional clock generators using multiple phase-locked loops (PLLs) often face challenges such as high-power consumption and increased chip area. In contrast, employing multiple fractional output dividers (FODs) driven by a single PLL provides a more compact and power-efficient alternative. FODs can be implemented using either digital-to-time converters (DTCs) [1]–[3] or digital-to-phase converters (DPCs) [4]. Among these, DTC-based FODs are commonly adopted due to their superior power efficiency and reduced area requirements. However, DTC-based FODs are prone to variations in process, voltage, and temperature (PVT), and any gain error or integral nonlinearity (INL) in the DTC can significantly degrade jitter performance. To calibrate the gain and INL of the DTC, a reference clock$(\mathrm{F}_{\text{ref}}$is required to detect these errors, as depicted in Fig. 8.6.1 (top left). Previous methods have utilized additional delay-complementary DTCs [1] or pulse-to-voltage converters [2] to generate$\mathrm{F}_{\text{ref}}$for DTC gain calibration. However, these techniques often neglect DTC INL, achieving only limited spur performance of approximately -55dBc [1] [2]. Although the background gain and INL calibration based on an auxiliary PLL...