An Ultra Low Voltage Energy Efficient Level Shifter With Current Limiter and Improved Split-Controlled Inverter

作者：Chao Wang, Yang Wei Lim, Yuxin Ji, Jiajie Huang, Wangzilu Lu, Fakhrul Zaman Rokhani, Yehea Ismail, Yongfu Li · 发表于：IEEE Transactions on Circuits & Systems II Express Briefs · 年份：2024 · DOI：10.1109/tcsii.2024.3379448 · 被引用次数：12 · 研究领域：Semiconductor materials and devices、Low-power high-performance VLSI design、Advancements in Semiconductor Devices and Circuit Design

This paper introduces an improved Wilson current mirror level shifter (WCMLS) circuit designed in CMOS 55 nm technology, optimized for ultra-low voltage applications. We aim to balance speed, power, and area by employing specific architectural choices in its pull-up and pull-down networks. The pull-up network (PUN) employs a Wilson current mirror to effectively reduce static current. The pull-down network (PDN) incorporates a diode-connected P-type transistor as a current limiter, further reducing static power consumption. An improved split-controlled inverter is introduced as the output driver to further minimize both static and short-circuit currents. The proposed level shifter can operate at a minimum VDDL of 100 mV at VDDH = 1.2 V and 1 MHz input frequency. Performance comparison with prior works reveals a significant performance improvement in terms of delay, power-delay product (PDP), and energy-delay product (EDP), with a delay of 4.79 ns, a PDP of 355 ns*nW, and an EDP of 326 fJ*ns when operating in a conversion range of 0.3 -1.2 V, making it a robust choice for energy-efficient ultra-low voltage level shifting applications.