Recent Advances and Trends in Chiplet Design and Heterogeneous Integration Packaging

作者：John Hon-Shing Lau · 发表于：Journal of Electronic Packaging · 年份：2023 · DOI：10.1115/1.4062529 · 被引用次数：77 · 研究领域：3D IC and TSV technologies、Electronic Packaging and Soldering Technologies、Nanofabrication and Lithography Techniques

Abstract In this study, chiplet design and heterogeneous integration packaging, especially (a) chip partition and heterogeneous integration driven by cost and technology optimization, Figs. 1(a) and 1(b) chip split and heterogeneous integration driven by cost and yield, Figs. 1(b) and 1(c) multiple system and heterogeneous integration with thin-film layers directly on top of a build-up package substrate, Figs. 1(c) and 1(d) multiple system and heterogeneous integration with an organic interposer on top of a build-up package substrate, Figs. 1(d) and 1(e) multiple system and heterogeneous integration with through-silicon via (TSV) interposer on top of a build-up package substrate, Fig. 1(e), will be investigated. Figures 1(c)–1(e) are driven by formfactor and performance. Emphasis is placed on their advantages and disadvantages, design, materials, process, and examples. Some recommendations will also be provided.