STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse

作者：Jinshan Yue, Yongpan Liu, Zhe Yuan, Xiaoyu Feng, Yifan He, Wenyu Sun, Zhixiao Zhang, Xin Si, Ruhui Liu, Zi Wang, Meng‐Fan Chang, Chunmeng Dou, Xueqing Li, Ming Liu, Huazhong Yang · 发表于：IEEE Journal of Solid-State Circuits · 年份：2022 · DOI：10.1109/jssc.2022.3148273 · 被引用次数：67 · 研究领域：Advanced Memory and Neural Computing、Ferroelectric and Negative Capacitance Devices、Advanced Neural Network Applications

Computing-in-memory (CIM) is a promising architecture for energy-efficient neural network (NN) processors. Several CIM macros have demonstrated high energy efficiency, while CIM-based system-on-a-chip is not well explored. This work presents a CIM NN processor, named STICKER-IM, which is implemented with sophisticated system integration. Three key innovations are proposed. First, a CIM-friendly block-wise sparsity (BWS) architecture is designed, enabling both activation-sparsity-aware acceleration and weight-sparsity-aware power-saving. Second, an adaptive kernel-/channel-order (KCO) mapping and intra-/inter-macro scheduling strategy is proposed to improve macro utilization and data reuse. Third, an efficient BWS-optimized CIM (BWS-CIM) macro with adaptive power-OFF ADCs is implemented. The STICKER-IM chip was fabricated in 65-nm CMOS technology. Experimental results show 5.8–158-TOPS/W average system energy efficiency on the sparse NN models. The macro/system-level energy efficiency is$4.23\times / 3.06\times $higher compared with the state-of-the-art CIM macros and processors.