An 0.8µm CMOS technology for high performance logic applications

作者：R. A. Chapman, R.A. Haken, David A. Bell, C.C. Wei, Robert Havemann, T.E. Tang, T.C. Holloway, R.J. Gale · 年份：1987 · DOI：10.1109/iedm.1987.191432 · 被引用次数：36 · 研究领域：Semiconductor materials and devices、Advancements in Semiconductor Devices and Circuit Design、Integrated Circuits and Semiconductor Failure Analysis

This paper reports on the process architecture and results of an 0.8µm 5V CMOS logic technology. The process, which is a factor of two faster than current 1.2µm CMOS technology, features seven optically patterned levels with 0.8µm geometries: isolation, gates, contacts, vias, TiN local interconnect (LI), and two metal levels.