Defect generation in trench isolation

作者：C.W. Teng, C. Slawinski, W. R. Hunter · 年份：1984 · DOI：10.1109/iedm.1984.190788 · 被引用次数：10 · 研究领域：Thin-Film Transistor Technologies、Silicon Carbide Semiconductor Technologies、Silicon and Solar Cell Technologies

Defect generation in silicon during trench isolation process has been studied. Several sources of defect generation have been identified using Secco etching. These include contamination from the redeposited oxide layer during the trench etch and the stress induced at trench corners during the trench cap and field oxidation. A Sealed Sidewall Trench (SST) isolation process has been developed which results in defect-free trench isolation structures. A key addition to the refill dielectrics in SST is the incorporation of nitride layer(s) for inhibiting excessive vertical bird's beaking.