UV-Assisted Minority Hole Trapping in 4H-SiC(n) Metal–Oxide–Semiconductor Capacitors with Al₂O₃/ AlO x /SiO₂ Gate Stacking

作者：Yao-Joe Yang, J. Hwu · 发表于：ECS Meeting Abstracts · 年份：2026 · DOI：10.1149/ma2026-01331520mtgabs

In this work, we investigate UV-assisted minority hole trapping in Al₂O₃/ AlO x /SiO₂/4H-SiC(n) MOS capacitors fabricated by combining intermittent spray hydrated oxidation with repetitive sprays (ISHO(r)) for the interfacial SiO₂ and anodization-after-evaporation for the AlO x and Al₂O₃ stacking dielectrics, as shown in Fig 1 . The AlO x layer was formed with a small voltage (15V) and a shorter ANO time (30min) but Al₂O₃ by a high voltage (30V) and a longer time (40min). The ISHO-based oxidation process has previously been demonstrated to form high-quality SiO₂/4H-SiC gate oxides [1] with low interface trap density and robust reliability, providing a solid foundation for further functional oxide stacking. C–V and I–V measurements in Figs. 2(a) an (b) show an effective oxide thickness of 15.3 nm and an interface trap density of ~8.2×10¹¹ cm⁻²eV⁻¹ near flatband and deep depletion under 0V, together with reverse a gate leakage current below 1 pA, confirming good oxide integrity. Under UVC illumination at the border of the device, the injected minority hole carriers are trapped and detrapped at the oxygen-deficient AlO x /SiO₂ interfacial region through a photon-enhanced carrier generation and field-assisted transport mechanism, as shown in Fig. 3 . After applying a −6 V/0.5 s stress for UV-assisted program (UVA-P) and a +2 V/0.5 s stress for UV-assisted erase (UVA-E), a stable C–V hysteresis is established. During UVA-P, as shown in Fig. 4(a) , the de...