PAICORE: A 1.9-Million-Neuron 5.181-TSOPS/W Digital Neuromorphic Processor With Unified SNN-ANN and On-Chip Learning Paradigm

作者：Yi Zhong, Yisong Kuang, Kefei Liu, Zi-Lin Wang, Shuo Feng, Guang Chen, Youming Yang, Xiu-Ping Cui, Qiankun Wang, Jian Cao, Song Jia, Y. Liang, Guangyu Sun, Xiao-Xin Cui, Ru Huang, Yuan Wang · 发表于：IEEE Journal of Solid-State Circuits · 年份：2025 · DOI：10.1109/jssc.2024.3426319 · 被引用次数：48 · 研究领域：Computer Science

The neuromorphic approach of fulfilling brain-like edge intelligence is confronted with three paramount challenges: 1) ever-increasing application demands versus insufficient on-chip resources; 2) diverse data sources and models versus heterogeneous computing paradigms; and 3) adaptation to real scenarios versus absence of on-chip learning. To bridge those gaps in the current research community, this article presents PAICORE, a 537.98-mm2 digital neuromorphic processor with a unified computing and learning paradigm. PAICORE is a scalable 1024-core design, integrating over 1.919 million neurons and 4.773 billion synapses on a single chip. PAICORE is implemented in globally asynchronous locally synchronous (GALS) style with a five-level fat up-down quadtree as dedicated network-on-chip (NoC) infrastructure and tiled 2-D chip array as inter-chip architecture. The distributed processing cores fuse the hybrid spiking neural network (SNN), artificial neural network (ANN), and on-chip spike-timing-dependent plasticity (STDP) learning models into a unified description by modular-level reconfiguration. PAICORE achieves the peak performance of 20.74 TSOPS, 41.49 TOPS, and 115.25 GSOPS, with the best energy efficiency of 5.181 TSOPS/W, 10.372 TOPS/W, and 1.222 TSOPS/W for SNN, ANN, and on-chip learning paradigms, respectively. Benefiting from the PAIFLOW software framework, PAICORE hardware platform can be equivalently simulated and efficiently programmed in a large-scale deployment, in...