An Approximate Multiplier for FPGA-based Izhikevich SNN Hardware Implementation

作者：Juli Yang, Lei Wang · 发表于：International Journal of High Speed Electronics and Systems · 年份：2025 · DOI：10.1142/s0129156426400173

This paper proposes an FPGA-optimized approximate multiplier specifically designed for spiking neural networks (SNNs) using the Izhikevich neuron model. Leveraging Mitchell-based and folded multiplication schemes, the multiplier achieves significant reductions in resource usage and power consumption with minimal accuracy degradation. Simulation and FPGA implementation results validate its efficacy, showing only slight decreases in MNIST classification accuracy (from 96.12% to 93.03%), making it highly suitable for embedded neuromorphic systems requiring low-power, resource-efficient computations.