WSC Optimizer: An Optimization Tool for Wafer-Scale Chip Architecture Exploration

作者：Wenbo Zhang, Bo Ding, Shuai Wei, Qinrang Liu, Hong Yu, Ke Song, Wei Guo, Bo Mei, Rui Zheng · 发表于：ENGINEERING Information Technology & Electronic Engineering · 年份：2026 · DOI：10.1631/eng.itee.2025.0008 · 研究领域：Interconnection Networks and Systems、3D IC and TSV technologies、Embedded Systems Design Techniques

In recent years, mature advanced packaging technologies have increasingly enabled the integration of multiple small dies into larger chips, while retaining chip-scale density and high-bandwidth interconnects. To address the inefficiencies of manual design and the challenges of heterogeneous optimization in wafer-scale chip (WSC) development, we systematically explore key factors in WSC architecture design. We integrate chip layout, operator mapping, and hardware-software codesign, and formulate the WSC architecture exploration problem as a multi-objective optimization task. First, we establish a hierarchical architecture model for WSCs, unifying the quantification of core constraints and interconnect topology constraints; second, we propose a hierarchical multi-objective collaborative optimization framework to jointly optimize physical constraints and task mapping communication patterns; finally, we develop a WSC optimizer toolchain that supports mixed-granularity simulation and generates optimal configurations for representative workloads. Experimental results demonstrate that compared with traditional computer architectures, the optimized architectures generated by our WSC optimizer achieve up to a 22× throughput improvement and a 5× latency reduction in application domains, such as cryptographic decryption and signal processing.