Signal integrity-aware multi-path design workflow for ultra-large-scale three-dimensional chips: A logic-on-memory stacking case study

作者：A. Li, Jianfei Jiang, Naifeng Jing, Yanan Sun, Zhigang Mao, Qin Wang · 发表于：Microelectronics Journal · 年份：2026 · DOI：10.1016/j.mejo.2026.107171 · 研究领域：3D IC and TSV technologies、Interconnection Networks and Systems、VLSI and FPGA Design Techniques