37.4 A 100Gb/s, 1.92pJ/b Aggregate 4-Lane Single-Ended NRZ Transceiver with 15dB Far-End Crosstalk Cancellation via On-Chip Feature Extraction and Classification in 16nm FinFET

作者：Xiaohui Lin, Ramin Javadi, Bella Bose, Tejasvi Anand · 年份：2026 · DOI：10.1109/isscc49663.2026.11409172 · 研究领域：Advancements in PLL and VCO Technologies、Radio Frequency Integrated Circuit Design、Low-power high-performance VLSI design

A low-power (1.92 pJ/bit), high-speed (100 Gb/s), equalizer-free, 4 -lane single-ended transceiver that leverages machine learning principles for crosstalk compensation is proposed. The transceiver uses feature extraction and on-chip classification. It achieves more than 0.2 UI horizontal opening for BER−12. The classification compensates the crosstalk from 3 aggressors and −15 dB far-end crosstalk power sum. The classification only accounts for 7% of the total transceiver power.