Automated Electro-Thermal Modeling Framework of Distributed Vertical Power Delivery Architectures with Substrate-Embedded Microfluidic Cooling

作者：Mingeun Choi, S. Krishnakumar, Yaroslav Popryho, Ramin Rahimzadeh Khorasani, Madhavan Swaminathan, Inna Partin-Vaisband, Satish Kumar · 年份：2025 · DOI：10.1109/itherm55376.2025.11235621 · 被引用次数：2 · 研究领域：3D IC and TSV technologies、Innovative Energy Harvesting Technologies、Low-power high-performance VLSI design

Next-generation high-performance computing (HPC) systems require power delivery solutions capable of sustaining beyond 1 kW per monolithic chip, with current densities expected to reach or exceed $2 \mathrm{~A} / \mathrm{mm}^{2}$. Distributed vertical power delivery (DVPD) architectures with integrated voltage regulators (IVRs) address this challenge by placing conversion stages closer to the processor, thereby reducing conduction losses. However, the interplay between temperature-dependent power dissipation and substrateembedded microfluidic cooling-particularly in 3D-stacked configurations where inner tiers have limited heat dissipation pathways-has been underexplored. This paper presents a PyAEDT-driven, automated electro-thermal modeling framework for 48 -to- 1 V DVPD architectures to accurately capture realistic power losses and pumping demands. Results demonstrate that ignoring electro-thermal feedback leads to significant underestimation of both power loss and IVR area. An electrical-only analysis predicts a total converter loss of 251.86 W, whereas integrating thermal effects raises this value to 285.91 W -an increase of about 13.5%. Likewise, IVR sizing grows by approximately 11% to mitigate elevated on-resistance and switching losses at higher temperatures. To maintain hot-spot temperatures below $85^{\circ} \mathrm{C}$, the required microfluidic flow rate must rise from $1 \mathrm{~g} / \mathrm{s}$, which is needed without considering electro-thermal interactions, ...