A Buffer-in-Loop NS-SAR ADC With CDAC Sharing-Error Feedback Structure and kT /C Noise Cancellation in 0.18-μm CMOS Technology

作者：Zirui Cui, Yiqun Shi, Qingqing Sun, Hao Zhu · 发表于：IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 年份：2025 · DOI：10.1109/tvlsi.2025.3619126 · 被引用次数：1 · 研究领域：Analog and Mixed-Signal Circuit Design、Advancements in PLL and VCO Technologies、Low-power high-performance VLSI design

Analog-to-digital converters (ADCs) with a wide input range and power efficiency are highly desired in various applications like robust industrial sensor data acquisition and bioelectrical signal monitoring, where successive approximation register (SAR) ADCs fabricated in mature process nodes account for a large proportion. This brief presents a buffer-in-loop (BIL) noise-shaping (NS) SAR ADC with a proposed CDAC sharing (CS)-error-feedback (EF) structure andkT/$C$cancellation method in 180 nm. Compared with traditional EF methods, this CS-EF NS scheme takes advantage of the simple BIL structure and reduces the input signal degradation problem due to charge sharing with the input signal or parasitic capacitor of the series EF capacitor in the signal path, and enhances the system robustness. Combined with thekT/$C$cancellation and coarse-to-fine conversion techniques, this BIL NS-SAR reduces the noise from sampling, buffer, and pre-amp. The measured peak signal-to-noise-and-distortion ratio (SNDR) is 74.9 dB with a bandwidth of 0.6 MHz, and this ADC consumes$218.7~\mu $W without the buffer.