A Machine Learning-Inspired PAM-4 Transceiver for Medium-Reach Wireline Links

作者：Ramin Javadi, Tejasvi Anand · 发表于：IEEE Journal of Solid-State Circuits · 年份：2025 · DOI：10.1109/jssc.2025.3616072 · 研究领域：VLSI and Analog Circuit Testing、Radio Frequency Integrated Circuit Design、3D IC and TSV technologies

This article presents an energy-efficient machine learning-inspired PAM-4 wireline transceiver that leverages data encoding at the transmitter (Tx) and feature extraction with classification at the receiver (Rx) to compensate for channel loss ranging from 13 to 26 dB, while maintaining the bit error rate (BER)-11. A new consecutive symbol-to-center (CSC) encoding scheme is proposed that assigns identifiable attributes to the data by moving all consecutive identical symbols (CISs) to the common-mode voltage (0 V) before transmission. Additionally, an on-chip decision-tree classifier is designed and implemented at the Rx back-end to learn both the channel and the CSC data encoding characteristics, enabling accurate detection of the original transmitted data in the presence of inter-symbol interference (ISI), with a latency of only 10 unit intervals (UIs). The decision-tree classifier operates with a low-power, feed-forward architecture without any feedback timing constraints, allowing the transceiver to communicate at 42 Gb/s with an energy efficiency of 1.43 pJ/b for compensating 26 dB loss. The proposed transceiver, fabricated in 16-nm FinFET, achieves a low energy/bit per channel loss of 0.055 pJ/b/dB, which is approximately$2{\times }$lower than prior conventional architectures.