WSe 2 /SnS 2 Heterostructure Arrays with Bilateral Accumulation Contact for Scalable p-Type Transistors and Logic Circuits

作者：Chenguang Zhu, Biyuan Zheng, Xingxia Sun, Yong Liu, Shuai Qin, Huawei Liu, Chao Ma, Xiong Xiong, Zuxin Chen, Dong Li, Anlian Pan · 发表于：Nano Letters · 年份：2025 · DOI：10.1021/acs.nanolett.5c03107 · 被引用次数：7 · 研究领域：2D Materials and Applications、MXene and MAX Phase Materials、Chalcogenide Semiconductor Thin Films

Field-effect transistors (FETs) based on two-dimensional (2D) materials hold great promise as essential components in next-generation electronics. However, achieving high-performance and large-scale production of p-type 2D FETs has remained a persistent challenge. In this study, SnS 2 is introduced as a tunneling contact layer, and performance-enhanced p-type WSe 2 FET arrays are fabricated by utilizing a self-aligned etching strategy based on WSe 2 /SnS 2 heterojunctions. Owing to the type-III energy band alignment between WSe 2 and SnS 2 forming a bilateral accumulation region at the heterojunction interface, the carrier injection is enhanced into WSe 2 through SnS 2 via a band-to-band tunneling process, which effectively reduces contact resistance and barrier height. The experimental results further demonstrate that, compared with normal WSe 2 FETs, the bilateral accumulation contact FET (BAC-FET) exhibits notable improvements in mobility, on-state current, and on/off ratio. Additionally, various logic circuits, including inverter, NOR, NAND, OR, and AND gates, are realized based on the BAC-FET arrays.