Analysis and Design of a Pipelined MASH Continuous-Time Delta-Sigma Modulator With 15.4 MHz-BW and 82.6 dB-SNDR

作者：Xinyu Qin, Yichen Jin, Mingqiang Guo, Guoxing Wang, Sai‐Weng Sin, Maurits Ortmanns, Yong Lian, Liang Qi · 发表于：IEEE Transactions on Circuits and Systems I Regular Papers · 年份：2025 · DOI：10.1109/tcsi.2025.3596608 · 被引用次数：4 · 研究领域：Analog and Mixed-Signal Circuit Design

This paper presents the design of a wideband pipelined multi-stage noise shaping (MASH) continuous time (CT) delta-sigma modulator (DSM). The quantization error of the overall$1^{\mathrm {st}}$-stage DSM is extracted as the input of the$2^{\mathrm {nd}}$stage, while the outputs of both stages are simply combined without using any digital filters. Overall, different shaping functions are generated for both QN without requiring any digital QN cancellation. Therefore, the pipelined MASH (PMASH) significantly mitigates QN leakage while retaining the decent loop stability of a traditional MASH. Additionally, several analyses have been made for the PMASH topology, e.g. the design guideline, the signal transfer function (STF), the robustness, etc. Clocked at 800MHz and enabling on-chip DAC calibration, the 65nm CMOS prototype with an exemplary 2-2 topology using multi-bit quantizers achieves 82.6 dB SNDR, 98.8 dB SFDR over 15.4 MHz BW at −0.5 dBFS 1.8 MHz input. The power consumption is 16.9 mW with 1.2V/1.5V supplies. It results in a competitive FoM${}_{\mathrm {S\vert SNDR}}$of 172.2 dB, while it avoids any off-chip calibrations.