First Demonstration of 9N+9P Complete Dipole Multi-V T s CMOS Integration with Atomic Interfacial Dipole Buffer Layer Technique in GAA NSFETs

作者：Ying Wei, Jiannian Yao, Yi Wang, Qiang Zhang, Shenyuan Yang, Liang Cao, Q. Li, Xin Zhang, Yang Zhang, Hong Yang, Junjie Li, H. Yin, Xiaolong Wang, Jun Luo · 年份：2025 · DOI：10.23919/vlsitechnologyandcir65189.2025.11075095 · 被引用次数：8 · 研究领域：Advancements in Semiconductor Devices and Circuit Design、Semiconductor materials and devices、Ferroelectric and Negative Capacitance Devices

For the first time, we reported one complete dipole CMOS integration with atomic interfacial dipole buffer layer (AIDBL) technique for WFM-free multi-$\mathrm{V}_{\mathrm{T}}$modulation technology. With novel dual dipole-first integration process, various dipole tuning and AIDBL linear$\mathrm{V}_{\mathrm{T}}$modulation capabilities, the experimental CMOS integration on GAA NSFETs were successfully established and the devices achieved symmetric 9N+9P level multi-$\mathrm{V}_{\mathrm{T}}\mathrm{s}$within ~800 mV, which providing one promising method to effectively reduce challenging$\mathrm{T}_{\text{sus}}$space for WFM filling and then enhance the transistor driving performance for future transistor technology.