First Experimental Demonstration of Dual-Sided N/P FETs in Filp FET (FFET) on 300 mm Wafers for Stacked Transistor Technology in Sub-1nm Nodes

作者：Heng Wu, Weihai Bu, Yandong Ge, Yanbang Chu, Jiacheng Sun, Jianxiang Jin, Yongqin Wu, Ye Ren, Falong Zhou, Lijie Zhang, Jack Wu, Ming Li, Jin Kang, Runsheng Wang, Xin Zhang, Ru Huang · 年份：2025 · DOI：10.23919/vlsitechnologyandcir65189.2025.11075188 · 被引用次数：5 · 研究领域：Advancements in Semiconductor Devices and Circuit Design、3D IC and TSV technologies、Semiconductor materials and devices

For the first time, dual-sided devices in Flip FET (FEET) were successfully demonstrated on 300 mm wafers, on which the FFET's unique back-to-back stacking of frontside (FS) NFET and backside (BS) PFET were realized. A series of key process modules including wafer bonding, substrate thinning, channel profile optimization, litho overlay correction and BS performance tuning were successfully developed. As a result, FS NFET after flipping behaved well and decent BS PFET (LG of 30 nm, SS of 73.1 mV/dec, DIBL of 24 mV and on-off ratio of 107) was achieved, comparable to the FS NFET. Thanks to the separated processes on each side of the wafer, this work further validates the outstanding features of FFET: natural split-gate, good multi- Vr tunablity (~ 500 m V) and better process margin without challenging high aspect ratio vertical patterning as required by CFET. Moreover, dual-sided CMOS was also realized, proving the excellent extendibility of FFET. With the great benefits in process-friendliness, design flexibility and scalability as compared with CFET, FFET is validated to be a crucial candidate for logic nodes beyond 1 nm.