Key to Low Supply Voltage: Transition Region of Oxide Semiconductor Transistors

作者：Kamalesh Jana, Jiheong Kang, Shuhan Liu, Fabia F. Athena, Chi‐Hsiang Huang, Yalun Tang, Hong-Yu Chen, Balreen Saini, Jonathan Hartanto, Robert K. A. Bennett, Ann Persson, Shuang Li, Karen M. Neilson, Yong‐Min Lee, Kaitlyn Leitherer, Kenji Nomura, Paul C. McIntyre, Eric Pop, H.‐S. Philip Wong · 年份：2025 · DOI：10.23919/vlsitechnologyandcir65189.2025.11075003 · 被引用次数：10 · 研究领域：Semiconductor materials and devices、Advancements in Semiconductor Devices and Circuit Design

We study the voltage transition region (TR) from sub- to above-threshold of field-effect transistors (FETs) and characterize its width ($\mathrm{V}_{\text{TR}}$) which informs how much the supply voltage ($\mathrm{V}_{\text{DD}}$) can be reduced. The TR is significant in amorphous oxide semiconductor field-effect transistors (OSFETs) because the shallow traps in amorphous OS channels lead to large$\mathrm{V}_{\text {TR }}$. We introduce a$\mathrm{V}_{\text {TR }}$extraction scheme and identify four main sources of shallow traps (ST) in amorphous OSFETs. We design experiments to individually evaluate their impact on$\mathrm{V}_{\text {TR }}$and successfully devise four OSFET process/design knobs to minimize V TR. Our analysis is then extended to other prominent FETs in the literature, with crystalline channel FETs showing$\mathrm{V}_{\text{TR}}<80 \text{mV}$, in contrast to amorphous OSFETs with$\mathrm{V}_{\text {TR }}$ranging from 160 mV to as high as 1.1 V, highlighting that$\mathrm{V}_{\text{TR}}$in amorphous OSFETs is a critical challenge that must be addressed.