Complexity Reduced MLSE Equalization Assisted With Pattern-Integrated LUT for Bandwidth Efficient PAM-4 IM/DD Interconnection

作者：Shaonan Liu, Jun Ming, Junyuan Song, Hailian He, Yujia Mu, Yuyao Wen, Zhipei Li, Rui Wang, Bo Tian, Ze Dong, Xiangjun Xin · 发表于：Journal of Lightwave Technology · 年份：2025 · DOI：10.1109/jlt.2025.3587481 · 被引用次数：3 · 研究领域：Copper Interconnects and Reliability、3D IC and TSV technologies、Semiconductor materials and devices

The inter-symbol-interference (ISI) is the major impairment in bandwidth-efficient intensity modulation and direct detection (IM/DD) interconnection systems regarding simultaneous low power consumption and high cost-effectiveness. The ISI can be well compensated by advanced digital equalizer cooperated with maximum likelihood sequence estimation (MLSE), and look-up table (LUT) associated MLSE schemes. However, under severe ISI scenarios, the implementation complexity of the combined LUT and MLSE increases significantly as the memory length for the required LUT expands. In this paper, an MLSE scheme employing pattern-integrated LUT (PiLUT-MLSE) with a reduced stage profile is proposed and demonstrated in a bandwidth-efficient 4-level pulse amplitude modulation (PAM-4) IM/DD interconnection system. The intermediate symbols are shared in integrated patterns by simply counting the ISI between adjacent preceding and succeeding symbols to optimize the LUT size effectively. By doing so, the computational loads for subsequent MLSE path comparison and addition are significantly reduced with the assistance of the optimized PiLUT. The effectiveness of the proposed PiLUT-MLSE is validated using 112, 140, and 160 Gbit/s PAM-4 signals transmitted over distances of 2 km, 1 km, and 500 m standard single-mode fiber (SSMF), in a 3 dB bandwidth of 19 GHz. Experimental results performed in 112/140 Gbit/s PAM-4 system indicate that the PiLUT-MLSE significantly decreases the ISI impairments with 0...