An Easy-Driving Incremental Zoom ADC With Skipped Sampling Scheme and NS-SAR Quantizer

作者：Zongnan Wang, Lu Jie, Zichen Kong, Mingtao Zhan, Yi Zhong, Yuan Wang, Xiyuan Tang · 发表于：IEEE Journal of Solid-State Circuits · 年份：2025 · DOI：10.1109/jssc.2025.3576663 · 被引用次数：3 · 研究领域：CCD and CMOS Imaging Sensors、Analog and Mixed-Signal Circuit Design、Neuroscience and Neural Engineering

This article presents an incremental zoom analog-to-digital converter (ADC) for Internet-of-Things (IoT) applications. Unlike prior zoom ADC designs, a floating inverter amplifier (FIA)-assisted residue extraction scheme is proposed to maintain the residue voltage during loop filtering. It allows the ADC to skip repeated sampling operations between consecutive fine conversions, thus largely reducing the sampling time and driving cost. To speed up the conversion, a high-efficiency second-order single buffer embedded noise-shaping (NS) successive approximation register (SAR) is proposed as the fine quantizer, allowing a low conversion cycle of 32. Together with the amplifier-reused kT/C noise cancellation technique, the prototype ADC fabricated in a 28-nm CMOS realizes a 92.5-dB SNDR at 300 kS/s with a small input capacitor of 0.8 pF. With fully dynamic operation, the power consumption is only$160~{\mu}$W, leading to a superior Schreier figure of merit (FoM) of 182.2 dB.