A 0.055pJ/bit/dB 42Gb/s PAM-4 Wireline Transceiver with Consecutive Symbol to Center (CSC) Encoding and Classification for 26dB Loss in 16nm FinFET

作者：Ramin Javadi, Tejasvi Anand · 年份：2025 · DOI：10.1109/cicc63670.2025.10982737 · 被引用次数：2 · 研究领域：VLSI and Analog Circuit Testing、Semiconductor materials and devices、Advancements in Semiconductor Devices and Circuit Design

The growth of data-intensive applications such as large language AI models has increased the demand for higher data throughput in wireline links. Due to the bandwidth-limited nature of the wireline channel, increasing the data rates across the same physical distance of the communication channel results in more inter-symbol interference (ISI). Consequently, more channel equalization is required to compensate for ISI, which increases the energy/bit of the communication link. Researchers have discovered that machine learning (ML) inspired approaches [1]–[2] including feature extraction and classification provide a more efficient solution for compensating the channel loss compared to the conventional equalization techniques like FFE, DFE, and CTLEs [3]–[7]. However, the prior works on ML inspired links are limited to NRZ modulation only. In this work, we introduce an energy-efficient ML inspired transceiver that leverages feature extraction and classification to transmit encoded PAM-4 data across a wide range of channel loss (13dB to 26dB) while maintaining BER−11without using any conventional equalizers. Additionally, we propose a data encoding scheme, consecutive symbol to center encoding (CSC) to encode PAM-4 and provide identifiable attributes to the transmitted signal, which helps to increase the channel loss compensation range and reduce the complexity of the classifier. Since ISI is a deterministic non-ideality, the proposed decision-tree based classifier (on-chip) is desi...