A Power-Efficient Jitter-Insensitive 3.2GHz 1-bit CT ΔΣ ADC with Direct Charge Dump Feedback

作者：Yanquan Luo, Lu Jie, Nan Sun · 年份：2025 · DOI：10.1109/cicc63670.2025.10982938 · 被引用次数：3 · 研究领域：Analog and Mixed-Signal Circuit Design、CCD and CMOS Imaging Sensors、Neuroscience and Neural Engineering

Using a 1-bit quantizer (QTZ) in a multi-GHz CT$\Delta\Sigma$ADC is beneficial as a 1-bit DAC demands no mismatch calibration or DEM. Additionally, a 1-bit QTZ is simple, does not require offset calibration, and easy to drive. However, in a CT$\Delta\Sigma$ADC using an active RC integrator and a resistive/current-steering (R/I) 1-bit feedback (FB) (Fig. 1, top-left), OTA 1 needs to absorb the large feedback current$I_{\text{fb}}$, which dictates OTA 1's power [1]. Moreover, a 1-bit$\mathrm{R}/$I FB is sensitive to jitter. An FIR FB reduces$\mathrm{I}_{\text{fb}}$and jitter sensitivity [2], but suffers from inter-symbol interference (ISI). A time-interleaved (TI) FIR FB can address the ISI issue [3], but the calibration demand of gain mismatches among TI DAC slices erases the benefit of the mismatch-calibration/DEM free characteristic of a 1-bit DAC. Alternatively, switched capacitor (SC) FB can be used to suppress both jitter impact and ISI by feeding a packet of charge to the loop filter (LF) in an impulsive manner [4]. However, OTA1 needs to absorb the resulting high peak current (Fig. 1, top-right), which consumes more power than that with a R/I FB. Mainly due to the power-hungry OTA 1, Schreier FoM ($\text{FoM}_{\mathrm{S}})$of the state-of-the-art 1-bit, DAC-calibration/DEM-free CT$\Delta\Sigma$ADCs with the conventional FBs is below 165dB [1], [5], [6] while multi-bit CT$\Delta \Sigma$ADCs have achieved$\text{FoM}_{\mathrm{S}}$beyond 170dB [7] [8].