A 32GS/s 8b 16× Time-Interleaved Hybrid ADC with Self-Detection Offset Calibration, DLL-Based T LSB PVT Variation Calibration and VTC Gain Self-Tracking

作者：Hongzhi Liang, Jun Chang, Yixiao Luo, Zeyu Peng, Weimin Zhou, Li Dang, Yue Cao, Haolin Han, Yi Shen, Lianxi Liu, Ruixue Ding, Zhangming Zhu · 年份：2025 · DOI：10.1109/cicc63670.2025.10983486 · 被引用次数：4 · 研究领域：Analog and Mixed-Signal Circuit Design、CCD and CMOS Imaging Sensors、Advancements in Semiconductor Devices and Circuit Design

ADC-DSP-Based PAM-4 long-reach transceivers are a key enabler for the ever-increasing data throughput demands of generative Al. A higher input bandwidth in these applications necessitates the embedded time-interleaved (TI) ADCs operating at several to tens of GS/s with at least 5 ENOB. Since input signals are orderly distributed across the enormous parallel sub-channels, the sub-ADCs should offer a high sampling rate and efficiency in both area and power. The voltage-domain SAR-based sub-ADCs are a proven power-efficient architecture [1]–[4]. However, ultra-high-speed TI-SARs with an enormous interleaving factor suffer from the long interconnection routing lines, limiting the effective bandwidth. Recently, time-domain (TD) ADCs have shown promising speed features with a compact layout due to the highly digital structure [5], [6]. However, the inverter-based time-quantization step (TLSB) introduces PVT variations and mismatch issues, which are exacerbated in interleaved ADCs. It also poses a challenge for the voltage-to-time converter (VTC) to track the gain error caused by$\mathrm{T}_{\text{LSB}}$variations. Thus, efficient and practical calibration mechanisms are essential for TI TD-ADCs to fully exploit the speed advantages of time-domain operation. A Tl hybrid SAR+ TDC with three on-chip calibrations is presented in this work. Inspired by the multi-phase clock generation scheme [7], [8], the$\mathrm{T}_{\text{LSB}}$variation can be calibrated by a delay-locked loop (DLL). ...