An area-efficient memristor-based trimming circuit for current reference with temperature coefficient optimization capability

作者：Tianhang Liang, Xiangrui Li, Zhigang Li, Haoyu Li, G. Chen, Yi‐Hao Chen, Huaxiang Lu · 发表于：IEICE Electronics Express · 年份：2025 · DOI：10.1587/elex.22.20250210 · 被引用次数：5 · 研究领域：Advanced Memory and Neural Computing、Ferroelectric and Negative Capacitance Devices、CCD and CMOS Imaging Sensors

With the widespread use of analogue circuits, current reference (CR) trimming has become an increasingly important issue. Therefore, finding a reliable and area-efficient trimming method becomes more and more critical. In this paper, a novel area-efficient memristor-based trimming circuit for current reference (CR) with temperature coefficient optimization capability is proposed. The proposed trimming core circuit uses only the source-degraded current mirror embedded in the memristors, thus achieving a significant area reduction.The circuit produces an output of approximately 5.2 μA, and test results show a calibrated output temperature coefficient (TC) of less than 75 ppm/°C over the temperature range of -20°C to 120°C, with a linearity of 4.3% /V over 2.2 to 4 V. The circuit implementation uses 0.18-μm CMOS technology. The layout area is less than 0.0016 mm2, representing average area savings of 84.3% over the current state of the art in trimming circuits.