DPFEE-Net: Enhancing Wafer Defect Classification Through Dual-Path Neural Architecture

作者：Hongxu Li, Jie Ren, Teng Wu, Yonghong Zhang, Jianhua Chang, Hongxin Yang, Ronghua Chi · 发表于：IEEE Transactions on Semiconductor Manufacturing · 年份：2025 · DOI：10.1109/tsm.2025.3564051 · 被引用次数：3 · 研究领域：Industrial Vision Systems and Defect Detection、Integrated Circuits and Semiconductor Failure Analysis、Advancements in Photolithography Techniques

Wafer defect detection and classification are essential for ensuring the quality of semiconductor wafers, optimizing production efficiency. However, existing methods often fail to process shallow and deep feature information concurrently, restricting their capacity to utilize multi-level features for accurate classification. To overcome this limitation, this paper introduces a novel dual-path architecture, DPFEE-Net, which integrates PeleeNet’s dense connection structure and multi-channel feature fusion techniques with the deep feature extraction capabilities of Convolutional Neural Networks (CNNs). By combining these two approaches, DPFEE-Net effectively captures both shallow and deep features, enhancing the detection of critical wafer surface defect patterns. Additionally, squeeze-and-excitation (SE) attention mechanism is incorporated, enabling the model to prioritize defect-prone areas in images, further improving classification accuracy. Experimental results demonstrate that DPFEE-Net achieves a remarkable average accuracy of 96.8% on the WM-811K dataset, surpassing existing methods such as WM-PeleeNet, WDD-SCA and MobileNetV2. Moreover, the model delivers superior detection performance with reduced computational complexity and parameter requirements, making it highly suitable for practical deployment in production environments.