FPGA Overlay processor for AI computing

作者：Lei He, Kun Wang, Chen Wu, Zhuofu Tao, Xiao SHI, Siyuan Miao, Shaoqiang Lu · 发表于：Scientia Sinica Informationis · 年份：2025 · DOI：10.1360/ssi-2024-0351 · 被引用次数：4 · 研究领域：Advanced Neural Network Applications、Software-Defined Networks and 5G、Embedded Systems Design Techniques

Currently, the computational complexity and update speed of neural networks are experiencing an explosive growth trend.To efficiently use neural networks on devices, technologies that accelerate neural networks have gained attention from both academia and industry.There are two categories of main neural network accelerators. The first is typically customized for specific types of neural networks to enhance inference performance.However, these schemes have certain limitations, such as poor scalability and a rather fixed computational data flow path.These limitations make these schemes inflexible in dealing with applications that require frequent switching of network models, especially in scenarios with high dynamic switching and real-time response.The second one is an instruction-based Overlay processing unit.The schemes of the Overlay processing unit first propose an instruction set for neural networks, which can easily be extended for coming networks.At the same time, a compiler is designed to perform optimization on the computation graph, allocation of computation, and scheduling of inputs from the software view.Meanwhile, the microarchitecture is designed for dataflow and parallelism optimizations from the hardware point of view.To this end, this study first analyzes the design philosophy and architectural features of customized neural network accelerators and Overlay processing units.Secondly, by comparing these two types of accelerators in terms of design scheme, flexibi...