A Valuable and Low-Budget Process Scheme of Equivalized 1 nm Technology Node Based on 2D Materials

作者：Yang Shen, Zhejia Zhang, Zhu‐Jun Yao, Mengge Jin, Jintian Gao, Yuhan Zhao, Wenzhong Bao, Yabin Sun, He Tian · 发表于：Nano-Micro Letters · 年份：2025 · DOI：10.1007/s40820-025-01702-7 · 被引用次数：10 · 研究领域：2D Materials and Applications、Ferroelectric and Negative Capacitance Devices、Graphene research and applications

Abstract Emerging two-dimensional (2D) semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level thickness. As the stacking process advances, the complexity and cost of nanosheet field-effect transistors (NSFETs) and complementary FET (CFET) continue to rise. The 1 nm technology node is going to be based on Si-CFET process according to international roadmap for devices and systems (IRDS) (2022, https://irds.ieee.org/ ), but not publicly confirmed, indicating that more possibilities still exist. The miniaturization advantage of 2D semiconductors motivates us to explore their potential for reducing process costs while matching the performance of next-generation nodes in terms of area, power consumption and speed. In this study, a comprehensive framework is built. A set of MoS 2 NSFETs were designed and fabricated to extract the key parameters and performances. And then for benchmarking, the sizes of 2D-NSFET are scaled to a extent that both of the Si-CFET and 2D-NSFET have the same average device footprint. Under these conditions, the frequency of ultra-scaled 2D-NSFET is found to improve by 36% at a fixed power consumption. This work verifies the feasibility of replacing silicon-based CFETs of 1 nm node with 2D-NSFETs and proposes a 2D technology solution for 1 nm nodes, i.e., “2D eq 1 nm” nodes. At the same time, thanks to the lower characteristic length of 2D semiconductors, the miniaturized 2D-NSFET achieves a 28%...