An 8b 10GS/s 2-Channel Time-Interleaved Pipelined ADC with Concurrent Residue Transfer and Quantization, and Automatic Buffer Power Gating

作者：Yunsong Tao, Mingtao Zhan, Mingyang Gu, Xiyu He, Yuxuan He, Zhishuai Zhang, Yi Zhong, Lu Jie, Nan Sun · 年份：2025 · DOI：10.1109/isscc49661.2025.10904751 · 被引用次数：3 · 研究领域：Analog and Mixed-Signal Circuit Design、Advancements in Semiconductor Devices and Circuit Design、Low-power high-performance VLSI design

High-speed (~10GS/s) medium-resolution (~8b) ADCs are key blocks for wideband applications. Time-domain ADCs can achieve 5GS/s single-channel speed [1], [2], but their reliance on matched gate delays leads to high sensitivity to PVT variations and device mismatches. By comparison, voltage-domain (flash/SAR/pipeline) ADCs are more robust against PVT and mismatches. However, flash ADCs are limited to 6b for their exponentially growing complexity with resolution [3]. SAR ADCs are efficient at 8b, but their limited single-channel speed ($\text{FoM}_{\mathrm{W}}$of 22fJ/conv-step, which outperforms comparable ADCs with$\mathrm{f}_{\mathrm{s}} > 6\text{GS}/\mathrm{s}$.