A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier

作者：Siyu Huang, Zhishuai Zhang, Xiyu He, Mingyang Gu, Yunsong Tao, Yi Zhong, Nan Sun, Lu Jie · 年份：2025 · DOI：10.1109/isscc49661.2025.10904746 · 被引用次数：9 · 研究领域：Semiconductor materials and devices、Analog and Mixed-Signal Circuit Design、Advancements in Semiconductor Devices and Circuit Design

In the analog front-end (AFE) of radio receivers, the base-band filter (BBF) before the ADC often occupies a significant area and noise contribution, especially when a Nyquist-sampling ADC is used and a sharp anti-aliasing BBF is thereby necessary (Fig. 18.7.1a). The continuous-time$\Delta\Sigma$modulator (CTDSM) relaxes the BBF by its intrinsic anti-aliasing (Fig. 18.7.1 b). However, it hits a “bandwidth wall” where its power consumption soars with bandwidth increment due to its closed-loop nature [1]–[3], impeding its applications in the next-gen wireless. The filter-embedded SAR ADC [4]–[5] is a promising alternative to the CTDSM. By incorporating a passive FIR/IIR filter into the CDAC, these SAR ADCs acquire anti-aliasing features with high efficiency and considerable area savings (Fig. 18.7.1c). Nevertheless, the filtering operation and SAR conversion intrinsically limit their sampling rate to tens of MHz, which is also inadequate for advanced wireless applications. To overcome these challenges, this work presents a filter-embedded pipe-SAR ADC (Fig. 18.7.1 d) for wide bandwidth (BW) and high efficiency. It introduces a progressive conversion scheme that mitigates the speed penalty of the filtering operation, and adopts a dynamic floating-charge transferrer (FCT) to achieve high-speed, high-efficiency and robust residue amplification. Fabricated in 28nm CMOS, the prototype filter-embedded ADC achieves 70.1 dB SNDR over an 80MHz BW with 4.9mW power consumption, converting...