MRAM Design-Technology-System Co-Optimization for Artificial Intelligence Edge Devices

作者：Win-San Khwa, Yi-Lun Lu, Sai Qian Zhang, Xiaoyu Sun, Syed Shakib Sarwar, Ziyun Li, Wu-Wun Chen, Jui-Jen Wu, Xiaochen Peng, Kerem Akarvardar, Ming-Yuan Song, Hung-Li Chiang, Xinyu Bao, Yu-Jen Wang, Wen-Ting Chu, Harry Chuang, Yu-Der Chih, Tsung-Yung Jonathan Chang, B. De Salvo, Chiao Liu, Meng‐Fan Chang · 年份：2024 · DOI：10.1109/iedm50854.2024.10873467 · 被引用次数：4 · 研究领域：Manufacturing Process and Optimization

STT-MRAM shows great promise for use in artificial intelligence (AI) edge devices due to its compact bitcell area and high endurance. However, it faces read challenges because of its low TMR and$\mathrm{R}_{\mathrm{p}}$. Conventional sense amplifiers have limitations in optimizing read energy and robustness while providing flexibility to exploit neural-net error tolerance. This article explores the design challenges of conventional sense amplifiers and examines how device parameters (TMR and$\mathrm{R}_{\mathrm{P}})$impact read performances. A novel capacitive-coupling sense amplifier is introduced to offer a new design space for balancing read energy and robustness. Combining the exploitation of neural-net error tolerance with sense amplifier and device co-design, a Design-Technology-System Co-Optimization (DTSCO) approach demonstrates a read energy reduction of 27.1 % to 45.3% with minimal inference accuracy degradation in edge AI applications.