Edge Continual Training and Inference with RRAM-Gain Cell Memory Integrated on Si CMOS

作者：Shuhan Liu, Robert M. Radway, Xinxin Wang, Filippo Moro, Jean-François Nodin, Koustav Jana, Shuting Du, Luke R. Upton, Wei-Chen Chen, Jian Chen, Haitong Li, F. Andrieu, Elisa Vianello, Priyanka Raina, Subhasish Mitra, H.‐S. Philip Wong · 年份：2024 · DOI：10.1109/iedm50854.2024.10873546 · 被引用次数：7 · 研究领域：Advanced Memory and Neural Computing、Ferroelectric and Negative Capacitance Devices、Integrated Circuits and Semiconductor Failure Analysis

This research presents the design and experimental validation of a novel RRAM-Gain Cell joint memory to facilitate efficient continual learning in edge devices, addressing the challenges of resource-constrained environments while supporting adaptive AI model updates. HfO2RRAM and Indium Tin Oxide (ITO) gain cell are monolithically integrated on 130 nm Si CMOS technology, enabling high-speed training and low-standby-power inference for edge devices. High-bandwidth on-chip data transfer can have bandwidth that is 90× state-of-the-art HBM3E and 211× PCIe 7.0, enabled by high-density monolithic 3D interconnections and high-speed transfer circuits within the integrated joint memory macro. The ALD ITO FET exhibits positive VTHof 0.67 V, excellent SS of 65 mV/dec, high on-current of 20 µA/µm, and low off-current of 5×10-18A/µm, as extracted from> 5,000 s retention. The joint memory macro consumes 78% less standby power and 95% less training energy for MobileBERT compared to SRAM with iso-capacity.