Monolithic 3D Integration of Multi-Layer CNT-CMOS/RRAM Macros for Mixed-Precision Analog-Digital Computing-in-Memory Architecture

作者：Yibei Zhang, Jianshi Tang, Yijun Li, Ningfei Ga, Lei Ga, Haitao Xu, Ran An, Huimin Yang, Zhengwu Liu, Chenglei Gu, Weihai Bu, Dong Wu, Bin Gao, He Qian, Huaqiang Wu · 年份：2024 · DOI：10.1109/iedm50854.2024.10873492 · 被引用次数：3 · 研究领域：Advanced Memory and Neural Computing、Ferroelectric and Negative Capacitance Devices、Semiconductor materials and devices

To implement large-scale AI model with computing-in-memory (CIM) technology, it is imperative to achieve both digital processor-equivalent high precision and analog CIM (A-CIM)-enhanced high computing efficiency, for which new CIM architectures with mixed precision are needed. In this work, for the first time, we present M3D-MP4, a Monolithic 3D integration chip featuring Mixed-Precision analog-digital CIM architecture with 4 functional layers: the 1st layer of Si CMOS for logic and control operations, the 2ndlayer of 128k-bit HfO2-based analog RRAM array for A-CIM, the 3rdand 4th layers of Ta2O5-based binary RRAM and carbon nanotube (CNT) CMOS for vertically stacked pseudo-digital CIM (PD-CIM) as well as cache and router arrays. The top 3 layers were fabricated using a low-temperature$( \leq 300^{\mathrm{o}}\mathrm{C})$process, enabling multiple layers of CNTFET/RRAM macros to be vertically stacked in the BEOL without performance degradation. The structural integrity and proper function of the fabricated M3D-MP4 chip was validated by extensive structural analysis and electrical measurements. Furthermore, system-level benchmarks show that the M3D-MP4 architecture could achieve 118.74x speed-up compared to its 2D counterpart and 16.92x lower energy than GPU.