2nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects Co-Optimized with 3DIC for AI, HPC and Mobile SoC Applications

作者：Geoffrey C-F Yeap, Shiwei Lin, Huiling Shang, H.C. Lin, Yu Chieh Peng, Mu‐Chun Wang, P. W. Wang, Ching‐Po Lin, K.F. Yu, Won‐Young Lee, H. Y. Chen, Da-Wei Lin, Byung-Do Yang, CC Yeh, Christopher T. Chan, J. Kuo, C-M Liu, T.K. Chiu, Mei Wen, T.L. Lee, CY Chang, R. Chen, P-H Huang, Chuanchuan Hou, Yuh‐Chieh Lin, F. C. Yang, Jou‐Kou Wang, S.K.H. Fung, Ryan Chen, C.H. Lee, TL Lee, Wei-Cheng Chang, DY Lee, Chao-Cheng Ting, Emmy T. Y. Chang, Hsuan‐Cheng Huang, HJ Lin, Ching-Hsiang Tseng, CW Chang, Kevin Huang, Yang Lu, Cheng‐Hsu Chen, Chi On Chui, K.h. Chen, Mong‐Hsun Tsai, Cheng-Chien Chen, Nan Wu, Huey‐Ling Chiang, Xinming Chen, Shuo Sun, J.T. Tzeng, Ken Wang, Yihao Peng, HJ Liao, Tao‐Hsing Chen, Ya-Chun Cheng, Jun-Hao Chang, Kenny Cheng-Hsiang Hsieh, Alan Cheng, Gang Liu, Ke Chen, HT Lin, KC Chiang, Chung-Hsien Tsai, Hua Wang, Wayne Huey‐Herng Sheu, John Yeh, Yung‐Ming Chen, CK Lin, Jay Wu, Min Cao, L. L. Juang, Fang‐I Lai, Yao-Ching Ku, S.M. Jang, Leiji Lu · 年份：2024 · DOI：10.1109/iedm50854.2024.10873475 · 被引用次数：50 · 研究领域：3D IC and TSV technologies、Semiconductor materials and devices、Parallel Computing and Optimization Techniques

A leading edge 2nm CMOS platform technology (N2) has been developed and engineered for energy-efficient compute in AI, mobile and HPC applications. This industry-leading N2 logic technology features energy-efficient gate-all-around nanosheet transistors, middle-of-line and backend-of-line interconnects with densest SRAM macro of$\sim 38\text{Mb}/\text{mm}^{2}$. N2 delivers a full node benefit from previous 3nm node [4] in offering 15% speed gain or 30% power reduction with$> 1.15\mathrm{x}$chip density increase. N2 platform technology, equipped with new Cu scalable RDL, flat passivation and TSVs, co-optimizes holistically with 3DFabric™ technology enabling system integration/scaling for AI/mobile/HPC product designs. N2 successfully met wafer-level reliability requirements and passed 1000hrs HTOL qual with high yielding 256Mb HC/HD SRAM, and logic test chip ($> 3\mathrm{B}$gates) consisting of CPU/GPU/ SoC blocks. Currently in risk production, N2 platform technology is scheduled for mass production in 2H'25. N2P, 5% speed enhanced version of N2 with full GDS compatibility, targets to complete qualification in 2025 and mass production in 2026.