A Sub-6 GHz Wideband Transceiver Chipset With Calibration-Friendly Harmonic Rejection RF Front-Ends

作者：Haoyu Bai, Ling Hao, Dong Wang, Ningyuan Zhang, Keer Gao, Jiaqi He, Jiazheng Zhou, Junhua Liu, Huailin Liao · 发表于：IEEE Transactions on Microwave Theory and Techniques · 年份：2025 · DOI：10.1109/tmtt.2025.3535587 · 被引用次数：6 · 研究领域：Radio Frequency Integrated Circuit Design、Microwave Engineering and Waveguides、Antenna Design and Analysis

This article presents a transmitter (TX) and receiver (RX) system operating in the 0.1–6 GHz frequency range with multi-protocol compatibility, which integrates local oscillator (LO) harmonic rejection (HR) radio frequency front-ends (RFFE) spanning 0.1–2.5 GHz, with frequency-adaptive calibration capabilities. In the HR-RFFE, programmable RC networks are deployed in both the TX and RX to achieve intermediate frequency (IF) domain HR and pre-calibration. An 8-phase LO signal generation, utilizing a D flip-flop (DFF) based chain, is employed to facilitate HR calibration. To mitigate HR degradation caused by LO phase errors, the TX employs a cross-connected Gilbert phase detector (PD) to assess the orthogonality of 90° shifted LO signals, enabling LO calibration. For the receiver, phase errors are directly calculated via the baseband (BB) output at a much lower frequency. Fabricated in 40-nm CMOS technology, the TX features a core area of 1.2 mm2, a programmable gain range of -12–26 dB, a P1dB compression point of 16.1 dBm, and a system efficiency of 25.9%. The third and fifth harmonic rejection ratios (HRRs) exceed 46.9 and 53.5 dBc, respectively. The receiver, which incorporates an integrated ADPLL, shows a core area of 1.4 mm2, a maximum gain of 68.4 dB, a minimum noise figure of 3.9 dB, and an odd-order HRR exceeding 71 dBc.