A 2–15 GHz 6-bit CMOS True Time Delay Chip With High Area Efficiency and Reduced Insertion Loss Variation

作者：Zhihua Wei, Jun‐Hao Liu, Xu Zhu, Pei‐Ling Chi, Ruimin Xu, Huaizong Shao, Tao Yang · 发表于：IEEE Transactions on Microwave Theory and Techniques · 年份：2025 · DOI：10.1109/tmtt.2025.3532476 · 被引用次数：5 · 研究领域：Interconnection Networks and Systems、VLSI and Analog Circuit Testing、Radio Frequency Integrated Circuit Design

In this article, a novel switched-line true time delay (TTD) circuit is presented using 65 nm CMOS process. It employs two different types of passive all-pass-networks (APNs), i.e., the series-inductor APN (SIAPN) and series-capacitor APN (SCAPN) with novel layout configuration based on S-shaped inductor to build the delay units. The S-shaped inductor which exhibits a self-canceled magnetic coupling feature makes it possible to embed different inductors in the APNs together without degrading the overall performance of the delay unit. Such operation can effectively avoid the area waste caused by the structural asymmetry between SCAPN and SIAPN in conventional layout design, thereby giving rise to an ultra-compact circuit design with high area efficiency. Meanwhile, novel single-pole-double-throw (SPDT) and double-pole-double-throw (DPDT) switches with asymmetrical magnitude responses are proposed. By setting proper circuit parameters, the switches can generate frequency-variant insertion loss with appropriate slope to compensate for the frequency-dependent loss difference between the delay path and reference path, and hence effectively reduce the loss-variation level among all delay states. Experimental results show that, with a core size of only$1.87\times 0.385$mm2, the designed TTD circuit can achieve a maximum delay tuning range of 315 ps and a minimum delay step of 5 ps within a broad frequency band ranging from 2 to 15 GHz. The corresponding area efficiency of the circui...