AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs

作者：Gao Mingzhe, Jieru Zhao, Zhe Lin, Wenchao Ding, Xiaofeng Hou, Feng Yu, Chao Li, Minyi Guo · 年份：2024 · DOI：10.1109/iccd63220.2024.00033 · 被引用次数：30 · 研究领域：Real-time simulation and control systems

Recently, the use of large language models (LLMs) for software code generation, e.g., C/C++ and Python, has proven a great success. However, LLMs still suffer from low syntactic and functional correctness when it comes to the generation of register-transfer level (RTL) code, such as Verilog. To address this issue, in this paper, we develop AutoVCoder, a systematic open-source framework that significantly improves the LLMs' correctness of generating Verilog code and enhances the quality of its output at the same time. Our framework integrates three novel techniques, including a high-quality hardware dataset generation approach, a two-round LLM fine-tuning method and a domain-specific retrieval-augmented generation (RAG) mechanism. Experimental results demonstrate that AutoVCoder outperforms both industrial and academic LLMs in Verilog code generation. Code and models are available at https://github.com/sjtu-zhao-lab/AutoVCoder.