Reconfigurable Logic and in‐Memory Computing Based on Electrically Controlled Charge Trapping in Dielectric Engineered 2D Semiconductor Transistors

作者：Dongxin Tan, Zheng‐Dong Luo, Qiyu Yang, Fei Xiao, Xuetao Gan, Dawei Zhang, Zhufei Chu, Fei Xue, Junpeng Zhang, Yinshui Xia, Yan Liu, Yue Hao, Genquan Han · 发表于：Advanced Functional Materials · 年份：2024 · DOI：10.1002/adfm.202417887 · 被引用次数：17 · 研究领域：Advanced Memory and Neural Computing、Ferroelectric and Negative Capacitance Devices、Semiconductor materials and devices

Abstract The co‐integration of logic, memory, synapse, and other essential functionalities into one single element with run‐time reconfigurability is explored as a promising approach for an efficient and flexible in‐memory computing platform. However, despite ample research focused on such reconfigurable semiconductor technology, it remains challenging to achieve a CMOS‐compatible device concept that is with simplified device structure, versatile functionalities, and efficient operation schemes. Here, a new type of run‐time electrically reconfigurable device is demonstrated based on dielectric‐engineered 2D semiconductor transistors. With an engineered semiconductor/charge‐trap layer/dielectric film heterostructure, the 2D charge‐trap transistor (CTT) resembles a simplified metal‐oxide‐semiconductor field‐effect transistor (MOSFET) structure. Both multilevel permanent charge trapping and transient voltage‐modulating capabilities can be realized in the 2D CTTs, giving rise to various switchable device function modes including non‐volatile memory, threshold voltage‐variable logic switch, and artificial synapse. Leveraging the monolithic integration of multiple 2D CTTs and time‐sequential reconfigurable operation strategy, high‐performance logic inverter and non‐volatile ternary content‐addressable memory (TCAM) with compact architecture can be created. The performance of the 2D CTTs in synapse mode is evaluated with the simulation of the convolutional neural network, showing gr...