Evaluations of Gate Oxide Reliability in SiC MOSFETs Under Extremely High Gate Voltage Stress

作者：Jianbin Guo, Zhehong Qian, Hang Xu, Bangmin Zhu, Yafen Yang, David Wei Zhang · 发表于：IEEE Transactions on Device and Materials Reliability · 年份：2024 · DOI：10.1109/tdmr.2024.3478220 · 被引用次数：6 · 研究领域：Silicon Carbide Semiconductor Technologies、Semiconductor materials and devices、Advancements in Semiconductor Devices and Circuit Design

This study aimed to evaluate the reliability of Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) under extremely high gate voltage stress. The research results show that SiCMOS has certain robustness to extremely high gate voltage stress. After high positive bias stress (PBS) and high negative bias stress (NBS), degradation at room temperature is mainly caused by the injection of holes. At high temperatures, the increased interface state traps appear to play an important role in the degradation under PBS. Both C-V characteristics and the recovery of devices after stress are used to explain the degradation. Degradation under high PBS might be recoverable. After recovery, the threshold voltage$(V_{T})$shift is less than 0.1V. Whereas damage under high NBS is permanent and unrecoverable. Remarkably, the robustness of the device under test to extremely high gate voltage stress is also verified, especially extreme PBS.