FastIC+: An Analog Front-End including on-chip TDCs for fast timing detectors

作者：J. Mauricio, F. Bandi, A. Paternò, S. Gómez, J. M. Fernandez-tenllado Arribas, J. Alozy, R. Manera, A. Mariscal, Markus Piller, S. Portero, A. Pulli, A. Sanuy, J.J. Silva, R. Ballabriga, M. Campbell, D. Gascón · 年份：2024 · DOI：10.1109/nss/mic/rtsd57108.2024.10657159 · 被引用次数：1 · 研究领域：Analog and Mixed-Signal Circuit Design、Low-power high-performance VLSI design、CCD and CMOS Imaging Sensors

This work presents the 8-channel FastIC+, a low-power consumption and highly configurable multi-channel front-end ASIC with internal digitization, for the readout of photo-sensors with picosecond time resolution and intrinsic gain. This 65 nm technology ASIC can readout positive or negative polarity sensors and provides a digitized measurement of the arrival time and energy of the detected events with a power consumption of 12.5 mW per channel. When connected to FBK NUV-HD LF2 M0 SiPMs, the analog processing achieves a Single Photon Time Resolution of (151 ± 3) FWHM and a Coincidence Time Resolution (CTR) of (127 ± 3) ps, coupled to LYSO:Ce:0.2% Ca scintillators measuring 3.13 × 3.13 × 20 mm3(without the digital contribution). On-chip digitization is executed by a Time-to-Digital Converter driven by a Phase-Locked Loop generating a 1.28 GHz clock. Preliminary evaluation of the TDC, conducted on a packaged ASIC within a socket board, yielded a time resolution of 34 ps FWHM with a power consumption of 3.3 mW per channel, demonstrating minimal impact on the analog readout.