An Asynchronous Winner-Takes-All Arbitration Architecture for Tsetlin Machine Acceleration

作者：Tian Lan, Omar Ghazal, Shalamn Ojukwu, Komal Krishnamurthy, Rishad Shafik, Alex Yakovlev · 年份：2024 · DOI：10.1109/newcas58973.2024.10666312 · 被引用次数：4 · 研究领域：DNA and Biological Computing、VLSI and Analog Circuit Testing、Ferroelectric and Negative Capacitance Devices

Machine Learning (ML) leverages algorithms to analyse and make classification predictions from input data. The Tsetlin Machine (TM) represents a distinctive ML algorithm for pattern recognition rooted in propositional logic and renowned for its straightforward logic, interpretability, and compatibility with hardware. This study introduces an innovative asynchronous architectural model to accelerate the TM's inference mechanism. Pioneering simple delay-race logic, this model diverges from TM's conventional arithmetic logic operations. The architecture comprises two modules: the class race module, which calculates the Hamming distance between the binary vectors of clauses using a delay mapping strategy in the temporal domain, and the asynchronous winner-takes-all (WTA) arbitration module, which determines the final classification based on this Ham-ming distance. This design utilises asynchronous four-phase “handshake” logic, characterised by quasi-delay insensitivity. This architecture achieves superior energy efficiency, operational speed, and robustness by leveraging an event-driven approach that obviates the need for a global clock.