A 32Gb/s 0.36pJ/bit 3nm Chiplet IO Using 2.5D CoWoS Package with Real-Time and Per-Lane CDR and Bathtub Monitoring

作者：Juping Gu, Jun Ma, Jun Guo, Fei Guo, Desheng Liang, Yong Li, C Shen, Peng Gao, Xinyuan Zhang, Jinhua Ding, M. Sorna, H. Wang, Can Cui, James E. Troupe, P Metty, Ken Chang · 年份：2024 · DOI：10.1109/vlsitechnologyandcir46783.2024.10631527 · 被引用次数：8 · 研究领域：Semiconductor Lasers and Optical Devices、Advancements in PLL and VCO Technologies、Photonic and Optical Devices

This work presents a high density single-ended NRZ Chiplet IO in 3nm CMOS technology over 2.5D CoWoS interposer of up to 2mm trace length, with a total of 216 data lanes running simultaneously at 32Gb/s/wire. The 2mm channel insertion loss and crosstalk at Nyquist frequency are −2.4dB and −18.1dB respectively. The RX features a real-time per-lane CDR and bathtub monitor, enabling optimal sampling point adaptation as well as tracking of phase drift over voltage and temperature. With all lanes toggling, the PHY achieves 3.84T/mm beach front density while consuming 0.36pJ/bit. The worst lane measures 0.342UI opening at BER of le-12 and interpolated 0.331UI opening at BER of le-15 when running at 32Gb/s. 25Gb/s results are also presented as a low power option.